When the core is generated using the Vivado Design Suite, a demonstration test bench is created. This is a simple VHDL test bench that exercises the core.
The demonstration test bench source code is one VHDL file: demo_tb/tb_<component_name>.vhd in the Vivado output directory. The source code is comprehensively commented.
Note: For native Floating-point and Fixed-point SSR>1,
the test bench file type should be set to VHDL-2008 in the Vivado project.