Core Overview - 9.1 English - PG109

The FFT core computes an N -point forward DFT or inverse DFT (IDFT) where N can be 2^m and m = 3–16.

For fixed-point inputs, the input data is a vector of N complex values represented as dual b_x -bit twos-complement numbers, that is, b_x bits for each of the real and imaginary components of the data sample, where b_x is in the range 8 to 34 bits inclusive. Similarly, the phase factors b_w can be 8 to 34 bits wide.

For pseudo single-precision floating-point inputs, the input data is a vector of N complex values represented as dual 32-bit floating-point numbers with the phase factors represented as 24- or 25-bit fixed-point numbers.

For native single-precision floating-point inputs, the input data is a vector of N complex values where each of the real and imaginary component is represented as a 32-bit single precision floating point number. This input data format is available on Versal adaptive SoC devices.

All memory is on-chip using either block RAM or distributed RAM. The N element output vector is represented using b_y bits for each of the real and imaginary components of the output data. Input data is presented in natural order and the output data can be in either natural or bit/digit reversed order. The complex nature of data input and output is intrinsic to the FFT algorithm, not the implementation.

Four arithmetic options are available for computing the FFT:

• Full-precision unscaled arithmetic
• Scaled fixed-point, where you provide the scaling schedule
• Block floating-point (runtime adjusted scaling)
• Native single-precision floating-point

The point size N, the choice of forward or inverse transform, the scaling schedule and the cyclic prefix length are runtime configurable. Transform type (forward or inverse), scaling schedule and cyclic prefix length can be changed on a frame-by-frame basis. Changing the point size aborts any frame currently being processed. The config packet needs to be four cycles before the first frame data. For SSR>1 fixed-point and native floating-point inputs, runtime configuration is not supported.

Four architecture options are available: Pipelined Streaming I/O, Radix-4 Burst I/O, Radix-2 Burst I/O, and Radix-2 Lite Burst I/O. For SSR>1 fixed-point and native floating-point inputs, only Pipelined Streaming I/O architecture is supported. For detailed information about each architecture, see Architecture Options.

The FFT is a computationally efficient algorithm for computing a Discrete Fourier Transform (DFT) of sample sizes that are a positive integer power of 2. The DFT X (k), k = 0,…,N -1 of a sequence x(n), n = 0,…,N - 1 is defined as:

where N is the transform size and j = √-1. The inverse DFT (IDFT) is given by:

Super Sample Rate (SSR) is supported for the fixed-point inputs and native single-precision floating-point inputs. The supported values of SSR are 1, 2, 4, 8, 16, 32, and 64 for fixed-point inputs, and 2, 4, 8, 16, 32, and 64 for native floating-point inputs. In SSR mode, SSR number of samples are processed per clock cycle.