The demonstration test bench performs the following tasks:
- Instantiate the core
- Generate two input data tables containing complex sinusoids of different frequencies
- Generate a clock signal
- Drive the core clock enable and reset input signals (if present)
- Drive the core input signals to demonstrate core feature
- Checks that the core output signals obey AXI protocol rules (data values are not checked to keep the test bench simple)
- Provide signals showing the separate fields of AXI TDATA and TUSER signals
The demonstration test bench drives the core input signals to demonstrate the features and modes of operation of the core. The complex multiplier is treated as a mixer that combines two complex sinusoids with different but similar frequencies, but opposite sign and different amplitude. The output of the core is therefore a complex sinusoid with a frequency equal to the difference in frequencies of the inputs, that is, a much slower frequency. The input data is pre-generated and stored in data tables, and the test bench drives the core data inputs with the sinusoid data throughout the operation of the test bench.
The demonstration test bench drives the AXI handshaking signals in different ways, split into three phases. The operations depend on whether Blocking Mode or NonBlocking Mode is selected:
- Blocking Mode:
- Phase 1
- full throughput, all TVALID and TREADY signals are tied High
- Phase 2
- apply increasing amounts of backpressure by deasserting the TREADY signal of the master channel
- Phase 3
- deprive slave channel A of valid transactions at an increasing rate by deasserting its TVALID signal
- NonBlocking Mode:
- Phase 1
- full throughput, all TVALID and TREADY signals are tied High
- Phase 2
- deprive slave channel A of valid transactions at an increasing rate by deasserting its TVALID signal
- Phase 3
- deprive all slave channels of valid transactions at different rates by deasserting each of their TVALID signals