Port Descriptions - 6.0 English

Port Descriptions - 6.0 English - PG104

Complex Multiplier LogiCORE IP Product Guide (PG104)

Document ID

PG104

Release Date

2024-11-26

Version

6.0 English

Figure 1. Core Schematic Symbol

The following table describes the Complex Multiplier core ports as shown in the preceding figure.

Table 1. Core Signal Pinout
Name	I/O	Optional	Description
aclk	I	Yes	Rising-edge clock. The aclk signal is optional. It is not present when FlowControl is NonBlocking and MinimumLatency = 0.
aclken	I	Yes	Active-High clock enable (optional)
aresetn	I	Yes	Active-Low synchronous clear (optional, always take priority over aclken) aresetn should be asserted or deasserted for not less than two aclk cycles.
s_axis_a_tvalid	I	No	TVALID for channel A
s_axis_a_tready	O	Yes	TREADY for channel A
s_axis_a_tuser[A-1:0]	I	Yes	TUSER for channel A. Width selectable from 1 to 256 bits
s_axis_a_tdata[B-1:0]	I	No	TDATA for channel A. See TDATA Packing for internal structure and width.
s_axis_a_tlast	I	Yes	TLAST for channel A.
s_axis_b_tvalid	I	No	TVALID for channel B
s_axis_b_tready	O	Yes	TREADY for channel B
s_axis_b_tuser[C-1:0]	I	Yes	TUSER for channel B. Width selectable from 1 to 256 bits
s_axis_b_tdata[D-1:0]	I	No	TDATA for channel B. See TDATA Packing for internal structure and width.
s_axis_b_tlast	I	Yes	TLAST for channel B.
s_axis_ctrl_tvalid	I	Yes	TVALID for channel CTRL
s_axis_ctrl_tready	O	Yes	TREADY for channel CTRL
s_axis_ctrl_tuser[E-1:0]	I	Yes	TUSER for channel CTRL. Width selectable from 1 to 256 bits
s_axis_ctrl_tdata[7:0]	I	Yes	TDATA for channel CTRL. See TDATA Packing for internal structure and width.
s_axis_ctrl_tlast	I	Yes	TLAST for channel CTRL.
m_axis_dout_tvalid	O	No	TVALID for channel DOUT
m_axis_dout_tready	I	Yes	TREADY for channel DOUT
m_axis_dout_tuser[G-1:0]	O	Yes	TUSER for channel DOUT. Width is the sum of the enabled TUSER fields on input channels.
m_axis_dout_tdata[H-1:0]	O	No	TDATA for channel DOUT. See TDATA Packinginternal structure.
m_axis_dout_tlast	O	Yes	TLAST for channel DOUT.
All AXI4-Stream port names are lower case but for ease of visualization, upper case is used in this document when referring to port name suffixes, such as TDATA or TLAST. Width constants A to H are arbitrary variables, determined by GUI or configuration parameters.