The AMD LogiCORE™ IP Complex Multiplier core implements AXI4-Stream compliant, high-performance, optimized complex multipliers based on user-specified options.
The two multiplicand inputs and optional rounding bit are input on independent AXI4-Stream channels as slave interfaces and the resulting product output on an AXI4-Stream master interface.
Within each channel, operands and the results are represented in signed twos complement format. The operand widths and the result width are parameterizable.