The Complex Multiplier core provides a complex multiplication solution for two complex operands where each operand can be from 8 to 63 bits wide (integer) or 32 bits wide (float). The real and imaginary components of each operand must be the same width as each other, but the widths of the two operands are individually configured (integer_only). Options are provided to bias the implementation to the needs of the application. For instance, latency is configurable, implementation can use DSP Slices or LUTs and the algorithm can use a 3 or 4 multiplier solution which trades latency for resource. AXI4-Stream interfaces are provided, but if the full traffic management capabilities of AXI4-Stream interfaces are not required, the interfaces can be configured for no additional resource.