Examples: - 6.0 English - PG104

Complex Multiplier LogiCORE IP Product Guide (PG104)

Document ID
PG104
Release Date
2024-11-26
Version
6.0 English

If channels A and CTRL both have TUSER with widths of 5 and 8 bits respectively, the output TUSER is a suitably delayed concatenation of A and CTRL TUSER fields, 13 bits wide, with A in the least significant 5 bit positions (4 down to 0).

If B and CTRL have TUSER widths of 4 and 10 respectively, but A has no TUSER, DOUT TUSER (m_axis_dout_tuser) has the bits of B_TUSER (s_axis_b_tuser) suitably delayed in positions 3 down to 0 with CTRL_TUSER (s_axis_ctrl_tuser) bits, suitably delayed, in positions 13 down to 4.