Selects which control signals should be present on the core. These options are disabled when the core has a minimum latency of zero.
- ACLKEN
- Enables the clock enable (
aclken) pin on the core. All registers in the core are enabled by this signal. - ARESETn
- Enables the active-Low synchronous clear (
aresetn) pin on the core. All registers in the core are reset by this signal. This can increase resource use and degrade performance, as the number of SRL-based shift registers that can be used is reduced. aresetn always take priority overaclken. - Implementation Details Tab
- Click the Implementation Details tab to see an estimate of the DSP Slice resources used for a particular complex multiplier configuration. This value updates instantaneously with changes in the GUI, allowing trade-offs in implementation to be evaluated immediately.