The term Blocking means that operation execution does not occur until fresh data is available on all input channels. The full flow control of AXI4-Stream aids system design because the flow of data is self-regulating. Blocking or NonBlocking behavior is selected using the FlowControl parameter or GUI field. Data loss is prevented by the presence of back-pressure (TREADY), so that data is only propagated when the downstream datapath is ready to process the data.
The Complex Multiplier has two or three input channels and one output channel. When all input channels have validated data available, an operation occurs and the result becomes available on the output. If the output is prevented from off-loading data because TREADY is Low then data accumulates in the output buffer internal to the core. When this output buffer is nearly full the core stops further operations. This prevents the input buffers from off-loading data for new operations so the input buffers fills as new data is input. When the input buffers fill, their respective TREADYs are deasserted to prevent further input. This is the normal action of backpressure.
The three inputs are tied in the sense that each must receive validated data before an operation is prompted. Therefore, there is an additional Blocking mechanism, where at least one input channel does not receive validated data while others do. In this case, the validated data is stored in the input buffer of the channel. After a few cycles of this scenario, the buffer of the channel receiving data fills and TREADY for that channel is deasserted until the starved channel receives some data. The following figure shows both Blocking behavior and back-pressure. The first data on channel A is paired with the first data on channel B, the second with the second and so on. This demonstrates the Blocking concept. The diagram further shows how data output is delayed not only by latency, but also by the handshake signal DOUT_TREADY. This is back-pressure’ Sustained back-pressure on the output along with data availability on the inputs eventually lead to a saturation of the core buffers, leading the core to signal that it can no longer accept further input by deasserting the input channel TREADY signals. The minimum latency in this example is two cycles, but it should be noted that in Blocking operation latency is not a useful concept. Instead, as the diagram shows, the important idea is that each channel acts as a queue, ensuring that the first, second, third data samples on each channel are paired with the corresponding samples on the other channels for each operation.