Video Data - 8.2 English - PG103

Video Test Pattern Generator LogiCORE IP Product Guide (PG103)
Document ID
PG103
Release Date
2025-11-20
Version
8.2 English

The AXI4-Stream interface specification restricts TDATA widths to integer multiples of 8 bits. Therefore, any bit data must be padded with zeros on the MSB to form a N*8 bit wide vector before connecting to s_axis_video_tdata. Padding does not affect the size of the core. Similarly, data on the TPG output m_axis_video_tdata is packed and padded to multiples of 8 bits as necessary. Zero padding the most significant bits is only necessary for 10 and 12 bit wide data.

The following figure through Figure 2-6 explain the pixel mapping of AXI4-Stream interface with 2 pixels per clock and 10 bits per component configuration for all supporting color formats. Zero padding (bits [63:60]) is not shown in the figures. Given that TPG requires hardware configuration for 3 component video, the AXI4-Stream Subset Converter is needed to hook up with other IPs of 2 component video interface in YUV 4:2:2 and YUV 4:2:0 color format.

Refer to Upgrading, and AXI4-Stream Video IP and System Design Guide (UG934) for more information.

Figure 1. Dual Pixels per Clock, 10 bits per Component Mapping for RGB

Figure 2. Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:4:4

Figure 3. Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:2:2

Figure 4. Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:2:0 Even Line

Figure 5. Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:2:0 Odd Line