Synthesizable Example Design - Synthesizable Example Design - 8.2 English - PG103

The difference between the Synthesizable design and the Simulation example design is the use of the MicroBlaze microprocessor instead of the AXI VIP core as AXI master.

The locked port of AXI4-Stream to Video Out is connected to axi_gpio_lock core and MicroBlaze polls the corresponding register for a sign that the test passed.

Because this design runs on hardware, it demonstrates the accuracy of TPG cores running a large video frame.

The synthsizable example design requires both Vivado tools and the Vitis software platform.

The first step is to run synthesis, implementation and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware. In the window, select Include bitstream, select an export directory and click OK.

The remaining work is performed in the Vitis software platform. The TPG example design file can be found at Vitis directory: (<install_directory>/Vitis/data/embeddedsw/XilinxProcessorIPLib/drivers/v_tpg_v8_7/examples/

Example application design source files (contained within "examples" folder) are tightly coupled with the v_tpg example design available in Vivado Catalog.

vtpg_example.tcl automates the process of generating the downloadable bit and elf files from the provided example xsa file.

To run the provided Tcl script:

1. Copy the exported example design hdf file in the "examples" directory of the driver
2. Launch the AMD Software Command-Line Tool (xsct) terminal
3. cd into the examples directory.
4. Source the tcl file:

   xsct%>source vtpg_example.tcl

5. Execute the script:

   xsct%>vtpg_example <xsa_file_name.xsa>

   The Tcl script cript performs the following:

   • Create workspace
   • Create HW project
   • Create BSP
   • Create Application Project
   • Build BSP and Application Project

   After the process is complete, the required files are available in:

   bit file->vtpg_example_hw_platform/hw folder elffile vtpg_example.sdk/vtpg_example_design/{Debug/Release} folder

Next, perform the following steps to run the software application:

1. Open the Vitis application, and select Get Started > Set Workspace.
   
   
2. Create the platform component. Select Embedded Development > New Platform Component.
   Enter the component name and location, and click Next.
   
   
3. Browse and select the hardware design XSA file generated with Vivado.
   
   
4. Select the operating system, processor, and compiler.
   
   
5. Review the summary, and click Finish.
6. Build the platform by selecting Flow > Build.
7. Once the platform component is created, switch to the welcome panel, and Create Empty Embedded Application through Embedded Development > New Application Component.
8. Select Create Empty Embedded Application.
   
   
9. Choose the component name and location, and click Next.
10. Enter Embedded Application Name and Location.
    
    
11. In the Hardware tab, select the required platform, and click Next.
    
    
12. From the list of available domains, select your domain.
    
    
13. (Optional) Add source files, review the summary, and click Finish.
14. Import the required files.
15. If you skipped the previous step, import the source files into the application component.
    
    
16. To build the project, select Flow > Build. When prompted for Platform build, click Yes.
    
    
17. After the build completes, check the Output folder for the .elf file.
    
    

The example design test results are shown in terminal program.

For more information, visit https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html.

When executed on the board, the example application performs the following:

• Program Video Clock Generator to 1080p@60 Hz
• Program TPG0 and TPG1 to 1080p@60 Hz
• Check for Video Lock and report the status (PASS/FAIL) on UART
• Repeat Steps 1-3 for 4 KP@30 Hz and 4 KP@60 Hz