Synthesizable Example Design - 8.2 English - PG103

The difference between the Synthesizable design and the Simulation example design is the use of the MicroBlaze microprocessor instead of the AXI VIP core as AXI master.

The locked port of AXI4-Stream to Video Out is connected to axi_gpio_lock core and MicroBlaze polls the corresponding register for a sign that the test passed.

Because this design runs on hardware, it demonstrates the accuracy of TPG cores running a large video frame.

Figure 1. Synthesizable Example Block Design

The synthsizable example design requires both Vivado tools and the Vitis software platform.

The first step is to run synthesis, implementation and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware. In the window, select Include bitstream, select an export directory and click OK.

The remaining work is performed in the Vitis software platform. The TPG example design file can be found at Vitis directory: (<install_directory>/release/data/embeddedsw/XilinxProcessorIPLib/drivers/v_tpg_v8_3/examples/

Example application design source files (contained within "examples" folder) are tightly coupled with the v_tpg example design available in Vivado Catalog.

vtpg_example.tcl automates the process of generating the downloadable bit and elf files from the provided example xsa file.

To run the provided Tcl script:

1. Copy the exported example design hdf file in the "examples" directory of the driver
2. Launch the AMD Software Command-Line Tool (xsct) terminal
3. cd into the examples directory.
4. Source the tcl file

   xsct%>source vtpg_example.tcl

5. Execute the script

   xsct%>vtpg_example <xsa_file_name.xsa>

   The Tcl script cript performs the following:

   • Create workspace
   • Create HW project
   • Create BSP
   • Create Application Project
   • Build BSP and Application Project

   After the process is complete, the required files are available in:

   bit file->vtpg_example_hw_platform/hw folder elffile vtpg_example.sdk/vtpg_example_design/{Debug/Release} folder

Next, perform the following steps to run the software application:

1. Launch the Vitis software platform.
2. Set workspace to vtpg_example.SDK folder in prompted window. The Vitis project opens automatically. (If a welcome page shows up, close that page.)
3. Download the bitstream into the FPGA by selecting AMD Tools > Program FPGA. The Program FPGA dialog box opens.
4. Ensure that the Bitstream field shows the bitstream file generated by Tcl script, and then click Program.
   Note: The DONE LED on the board turns green if the programming is successful.
5. A terminal program (Hyper Terminal or PuTTY) is needed for UART communication. Open the program, choose appropriate port, set baud rate to 115200 and establish Serial port connection.
6. Select and right-click the application vtpg_example_design in Project_Explorer panel.
7. Select Run As > Launch on Hardware (System Debugger).
8. Select Binaries and Qualifier in window and click OK.

The example design test results are shown in terminal program.

For more information, visit https://www.xilinx.com/products/design-tools/vitis.html.

When executed on the board, the example application performs the following:

• Program Video Clock Generator to 1080p@60 Hz
• Program TPG0 and TPG1 to 1080p@60 Hz
• Check for Video Lock and report the status (PASS/FAIL) on UART
• Repeat Steps 1-3 for 4 KP@30 Hz and 4 KP@60 Hz