There are no IP specific restrictions on the maximum achievable clock frequency. The restriction is dependent on if the design can meet timing or not.
Meeting timing is dependent on the clock frequency selected, and is impacted by resource utilization, tool options, additional logic in the device and the version of tool used.
For more information, see AMD timing closure documentation as well as the fabric data-sheets below. The frequency ranges specified in these documents must be adhered to for proper transceiver and core operation.
- Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)
- Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)
- Kintex 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182)
- Virtex 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS183)
- Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS181)
- Zynq 7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Data Sheet: DC and AC Switching Characteristics (DS187)
- Zynq 7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100) Data Sheet: DC and AC Switching Characteristics (DS191)
- Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
- Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)
- Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
- Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
- Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)