| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family1 |
AMD Versal™ adaptive SoC, AMD UltraScale+™ Families, AMD UltraScale™ Architecture, 7 series. |
| Supported User Interface | AXI4-Lite, AXI4-Stream 2 |
| Resources | Performance and Resource Utilization web page |
| Provided with Core | |
| Documentation | Product Guide |
| Design Files | Not Provided |
| Example Design | Yes |
| Test Bench | Not Provided |
| Constraints File | XDC |
| Simulation Models | Encrypted RTL, VHDL, or Verilog Structural |
| Supported Software Drivers 3 | Standalone, V4L2 |
| Tested Design Flows 4 | |
| Design Entry Tools | Vivado Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) |
| Synthesis tool | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54536 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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