The master and slave AXI4-Stream video
interfaces use the
AP_CLK clock signal as their shared
clock reference, as shown in the following figure.
Figure 1. Example of AP_CLK Routing in an ISP Processing
Pipeline
The AXI4-Lite interface also uses the
AP_CLK pin as its clock source. The AP_CLK pin is shared between the AXI4-Lite and AXI4-Stream
interfaces.