User Parameters - 2.0 English - PG101

AXI Protocol Checker LogiCORE IP Product Guide (PG101)
Document ID
PG101
Release Date
2023-06-21
Version
2.0 English

The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).

Table 1. Vivado IDE Parameter to User Parameter Relationship
Vivado IDE Parameter/Value User Parameter/Value Default Value
Connection Protocol PROTOCOL AXI4
READ_WRITE Mode READ_WRITE_MODE READ_WRITE
Address Width ADDR_WIDTH 32
Data Width DATA_WIDTH 32
ID Width ID_WIDTH 0
AWUSER Width AWUSER_WIDTH 0
ARUSER Width ARUSER_WIDTH 0
WUSER Width WUSER_WIDTH 0
RUSER Width RUSER_WIDTH 0
BUSER Width BUSER_WIDTH 0
Maximum Outstanding Read Transactions MAX_RD_BURSTS 8
Maximum Outstanding Write Transactions MAX_WR_BURSTS 8
Maximum Number of Idle Cycles for AWREADY Monitoring 1 MAX_AW_WAITS 0 (disabled)
Maximum Number of Idle Cycles for ARREADY Monitoring 1 MAX_AR_WAITS 0 (disabled)
Maximum Number of Idle Cycles for WREADY Monitoring 1 MAX_W_WAITS 0 (disabled)
Maximum Number of Idle Cycles for RREADY Monitoring 1 MAX_R_WAITS 0 (disabled)
Maximum Number of Idle Cycles for BREADY Monitoring 1 MAX_B_WAITS 0 (disabled)
Maximum number of idle cycles for RVALID monitoring after AR command 1 MAX_CONTINUOUS_RTRANSFERS_WAITS 0 (disabled)
Maximum number of idle cycles for WVALID monitoring after AW command 1 MAX_CONTINUOUS_WTRANSFERS_WAITS 0 (disabled)
Maximum number of idle cycles for AWVALID monitoring after a W-channel burst completes 1 MAX_WLAST_TO_AWVALID_WAITS 0 (disabled)
Maximum number of idle cycles for BVALID monitoring after a write burst completes 1 MAX_WRITE_TO_BVALID_WAITS 0 (disabled)
Simulation Log Messaging Level
  • Quiet
  • Info
  • Error
  • Stop on error
  • Finish on error
 MESSAGE_LEVEL
  • 0
  • 1
  • 2
  • 3
  • 4
 2 (Error)
Xilinx Connection Checking of Supports Narrow Burst
  • No
  • Yes
 SUPPORTS_NARROW_BURST
  • 0
  • 1
 1 (Yes)
Xilinx Maximum Connection Burst Length MAX_BURST_LENGTH 256
Enable System Reset Interface
  • No
  • Yes
 HAS_SYSTEM_RESET
  • 0
  • 1
 0 (No)
Only check for bus-hang conditions between protocol-compliant IP
  • No
  • Yes
 LIGHT_WEIGHT
  • 0
  • 1
 0 (No)
Enable S_AXI status interface
  • No
  • Yes
 ENABLE_CONTROL
  • 0
  • 1
 0 (No)
Enable Mark_Debug on pc_status
  • No
  • Yes
 ENABLE_Mark_Debug
  • 0
  • 1
 1 (Yes)
Detect RD/WR SLVERR and DECERR
  • No
  • Yes
 CHK_ERR_RESP
  • 0
  • 1
 0 (No)
  1. The timeout check is disabled when the parameter is set to 0.