The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 06/21/2023 Version 2.0 | |
| NA | Editorial updates. |
| 06/15/2022 Version 2.0 | |
| NA | Editorial changes. |
| 04/04/2018 Version 2.0 | |
| NA |
|
| Product Specification | Removed table note markers from the notes column in the AXI4/AXI3 and AXI4-Lite Protocol Checks and Descriptions table. |
| 12/20/2017 Version 2.0 | |
| Design Flow Steps |
|
| 10/04/2017 Version 2.0 | |
|
|
| 06/07/2017 Version 1.1 | |
| Added simulation-only assertions. | |
| 04/05/2017 Version 1.1 | |
| NA |
|
| 10/05/2016 Version 1.1 | |
| NA | Updated “AXI_ERRS_RID” protocol support and description. |
| 11/18/2015 Version 1.1 | |
| NA | Added support for Ultrascale+ families |
| 04/01/2015 Version 1.1 | |
| User Parameters | Added the topic. |
| 12/18/2013 Version 1.1 | |
| NA | Added support for UltraScale+ architecture. |
| 10/02/2013 Version 1.1 | |
| NA | Added compatibility with AXI Interconnect v2.1. |
| Simulation | Added the topic. |
| Synthesis and Implementation | Added the topic. |
| 06/19/2013 Version 1.0 | |
| Parameter Checker Options |
|
| 12/18/2012 Version 1.0 | |
| NA | Initial release. |