Protocol Independent Port Descriptions - 2.0 English - PG101

AXI Protocol Checker LogiCORE IP Product Guide (PG101)
Document ID
PG101
Release Date
2023-06-21
Version
2.0 English

The following table lists the ports that apply to all protocols.

Table 1. Protocol Independent Port Descriptions
Signal Name Direction Default Width Description
aclk Input Required 1

Interface clock input.

Used by both the AXI PC Monitor interface, and the optional AXI4-Lite Control register slave interface.
aresetn Input Required 1

Interface reset input (active-Low).

Resets both the AXI PC Monitor interface and the optional AXI4-Lite Control register slave interface.
system_resetn Input Optional 1 System reset (active-Low).
pc_status Output 160 Active-High vector of protocol violations or warnings.
pc_asserted Output 1 Active-High signal is asserted when any bit of the pc_status vector is asserted.