Clocks and Resets - 2.0 English - PG101

AXI Protocol Checker LogiCORE IP Product Guide (PG101)
Document ID
PG101
Release Date
2023-06-21
Version
2.0 English

To resolve clocking and reset issues, verify these items:

  • Check that aclk is connected to the same clock that is driving both the Master and Slave interfaces.
  • Check that aresetn is connected to the same reset that is driving both the Master and Slave interfaces.
  • Ensure that both aresetn and system_resetn (if enabled) are connected to active-Low polarity.
  • Ensure that aresetn is both synchronously asserted and released on aclk.