AXI EMC LogiCORE IP Product Guide (PG100) - 3.0 English

Document ID: PG100
Release Date: 2024-12-11
Version: 3.0 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Module Descriptions
AXI4 Slave Interface
AXI4-Lite Interface
Memory Controller Unit
Byte Parity Logic
EMC Register
I/O Registers
Flash (Memory) Access through STARTUPE Primitive
Application
Licensing and Ordering
Product Specification
Standards Compliance
Performance
Maximum Frequencies
Resource Utilization
Port Descriptions
Register Description
PARITY ERROR ADDRESS Register (PARITY_ERR_ADDR_REG_x)
PSRAM/Flash Configuration Register (PSRAM_FLASH_CONFIG_REG_X)
Configuring the Micron Flash in Sync Burst Read Mode
Designing with the Core
General Design Guidelines
Address Map Description
Allowable Memory Combination
Memory Data Types and Organization
Connecting to Memory
Clocking Synchronous Memory
Address Bus, Data Bus, and Control Signal Connections
Connecting to SRAM
Example 1: Connection to 32-bit Memory Using Two IDT71V416S SRAM Parts
Connecting to Byte Parity Memory
Connection to 32-bit Memory Using IS61LVPS25636A Synchronous SRAM Parts
Connecting to Intel StrataFlash
Example 2: Connection to 32-bit Memory Using Two StrataFlash Parts in x16 Mode
Example 3: Connection to 32-bit Memory Using Four StrataFlash Parts in x8 Mode
Connecting to Spansion Page Mode Flash S29GL032N
Connecting to PSRAM
Software Considerations
Using the STARTUPE Primitive
STARTUP Primitive Included in Design
STARTUP Primitive is Not in Design
Timing Diagrams
Design Flow Steps
Customizing and Generating the Core
AXI Data Width
AXI ID Width
Maximum Data Width
No. of Memory Banks
Base Address
High Address
Flash (Memory) Access through STARTUP Primitive
Memory Type
Data Width
Parity
Delay Model
Read CE Low to Data Valid Period
Read Address Valid to Data Valid Period
Page Access Period
Read CE High to Data Bus HZ Period
Read OE High to Data Bus HZ Period
Write Cycle Period
Write Enable Minimum Pulse Width
Write Phase Period
Write WE High to Data Bus LZ Period
Write Recovery Period for Flash Memory
Enable Burst Mode for Micron Flash
Enable Internal Registers
User Parameters
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Implementing the Example Design
Example Design Directory Structure
Test Bench
Simulating the Example Design
Setting Up the Simulation
Simulation Results
Verification, Compliance, and Interoperability
Simulation
Hardware Testing
Migrating and Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Interface Debug
AXI4-Lite Interfaces
AXI4-Memory Mapped Interfaces
Additional Resources and Legal Notices
Support Resources
Finding Additional Documentation
References
Revision History
Please Read: Important Legal Notices

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