This appendix provides details about how this IP core was tested for compliance.
Simulation
The ECC core has been tested with AMD Vivado™ Design Suite and Mentor Graphics QuestaSim simulator.
Hardware Testing
The ECC core has been validated at 200 MHz on KC705 board using AMD Kintex™ 7 FPGA -2 speed grade device (325T). The core was configured for encoder, decoder, encoder/decoder modes across 4-128 data widths.