Test Bench - Test Bench - 2.0 English - PG092

This chapter contains information about the test bench provided in the AMD Vivado™ Design Suite.

The following figure shows a block diagram of the demonstration test bench for Encoder or Encoder/Decoder configuration.

The following figure shows a block diagram of the demonstration test bench for Decoder configuration.

To demonstrate the functionality of ECC core, a partner instance of ECC core in complementary mode is connected to the ECC core in example design. The demonstration test bench performs the following tasks:

1. Input clock signals are generated.
2. A reset is applied to the example design.
3. For Encoder/Decoder configuration, the ECC module in example design is configured as a Encoder.
4. Clock enable for the ECC core is generated, in cases where registering is involved.
5. ecc_correct_n signal is deasserted.
6. The traffic generator starts generating data for ten clock periods continuously.
7. The Error Insertion Logic inserts single- and double-bit errors alternatively in the encoded data.
8. The Traffic Checker checks the output data from the ECC Decoder. When a single-bit error or a double-bit error is not detected, the test bench errors out with ERROR: single/double bit error not detected in the console. When a single bit error is not corrected, the error message "ERROR: expected data mis-match = expected, actual" is issued at the console.
9. Ten transactions are showcased in the test bench. The test bench finishes with the message Test Completed Successfully.