The following tables show the resource utilization numbers for the ECC core
for the AMD Kintex™ 7 family and -1
speed grade of FPGAs. Benchmark values generate using the AMD Vivado™ Design Suite.
Table 1. Resource Utilization for Hamming Algorithm
| Features |
Frequency |
| Data Width |
Mode |
I/O Registering |
Output Registering |
Internal Pipeline |
Slices |
LUTs |
FFs |
| 32-bit |
Encoder |
0 |
0 |
0 |
9 |
28 |
0 |
| Decoder |
0 |
0 |
0 |
24 |
83 |
0 |
| Encoder/Decoder |
0 |
0 |
0 |
30 |
101 |
0 |
| Encoder |
1 |
0 |
0 |
14 |
28 |
32 |
| Decoder |
0 |
1 |
1 |
28 |
87 |
82 |
| Encoder/Decoder |
1 |
1 |
1 |
37 |
100 |
131 |
| 64-bit |
Encoder |
0 |
0 |
0 |
18 |
53 |
0 |
| Decoder |
0 |
0 |
0 |
43 |
155 |
0 |
| Encoder/Decoder |
0 |
0 |
0 |
49 |
169 |
0 |
| Encoder |
1 |
0 |
0 |
34 |
53 |
64 |
| Decoder |
0 |
1 |
1 |
54 |
164 |
148 |
| Encoder/Decoder |
1 |
1 |
1 |
83 |
180 |
231 |
Table 2. Resource Utilization for Hsiao Algorithm
| Features |
Frequency |
| Data Width |
Mode |
I/O Registering |
Output Registering |
Internal Pipeline |
Slices |
LUTs |
FFs |
| 64-bit |
Encoder |
0 |
0 |
0 |
14 |
47 |
0 |
| Decoder |
0 |
0 |
0 |
47 |
164 |
0 |
| Encoder/Decoder |
0 |
0 |
0 |
53 |
184 |
0 |
| Encoder |
1 |
0 |
0 |
33 |
47 |
64 |
| Decoder |
0 |
1 |
1 |
65 |
171 |
139 |
| Encoder/Decoder |
1 |
1 |
1 |
83 |
172 |
223 |
| 128-bit |
Encoder |
0 |
0 |
0 |
29 |
100 |
0 |
| Decoder |
0 |
0 |
0 |
88 |
299 |
0 |
| Encoder/Decoder |
0 |
0 |
0 |
93 |
313 |
0 |
| Encoder |
1 |
0 |
0 |
71 |
102 |
128 |
| Decoder |
0 |
1 |
1 |
119 |
292 |
268 |
| Encoder/Decoder |
1 |
1 |
1 |
226 |
293 |
416 |