Product Specification - Product Specification - 2.0 English - PG092

ECC LogiCORE IP Product Guide (PG092)
Document_ID
PG092
Release_Date
2026-07-22
Version
2.0 English

The AMD LogiCORE™ IP ECC core is ideal for robust data transmission with error correction and checking capabilities. The adaptable core supports Hamming and Hsiao algorithms for Single Error Correction and Double Error Detection (SEC-DED) error correction codes (ECC).

Figure 1. ECC Block Diagram
Check Bit Generator ecc _ data _ out ecc _ chkbits _ out ecc _ data _ in Check Bit Generator Syndrome Generator Error Mask Generation / Single Bit Correction ecc _ correct _ n ecc _ sbit _ err ecc _ chkbits _ in ecc _ data _ in ecc _ encode Check Bit Generator Syndrome Generator Error Mask Generation / Single Bit Correction ecc _ correct _ n ecc _ dbit _ err ecc _ chkbits _ in ecc _ data _ in ecc _ data _ out ecc _ sbit _ err ecc _ dbit _ err ecc _ data _ out ecc _ chkbits _ out ECC Encoder ECC Decoder ECC Encoder / Decoder when encode : disable correction when decode : allow correction when encode : generate check bits when decode : generate syndrome X13097