This section details the performance information for various core configurations.
Maximum Frequencies
The following tables show the performance numbers for the ECC core for the AMD Kintex™ 7 family and -1 speed grade of FPGAs. Benchmark values generate using the AMD Vivado™ Design Suite. In the benchmark designs, the core is encased in a wrapper with input and output registers to remove the effects of I/O delays from the results.
| Features | Frequency | |||
|---|---|---|---|---|
| Data Width | Mode | I/O Registering | Internal Pipeline | MHz |
| 32-bit | Encoder | 1 | 0 | 550 |
| Decoder | 1 | 0 | 350 | |
| Encoder/Decoder | 1 | 0 | 325 | |
| Encoder | 1 | 1 | 550 | |
| Decoder | 1 | 1 | 500 | |
| Encoder/Decoder | 1 | 1 | 475 | |
| 64-bit | Encoder | 1 | 0 | 500 |
| Decoder | 1 | 0 | 290 | |
| Encoder/Decoder | 1 | 0 | 270 | |
| Encoder | 1 | 1 | 500 | |
| Decoder | 1 | 1 | 440 | |
| Encoder/Decoder | 1 | 1 | 420 | |
| Features | Frequency | |||
|---|---|---|---|---|
| Data Width | Mode | I/O Registering | Internal Pipeline | MHz |
| 64-bit | Encoder | 1 | 0 | 500 |
| Decoder | 1 | 0 | 320 | |
| Encoder/Decoder | 1 | 0 | 270 | |
| Encoder | 1 | 1 | 500 | |
| Decoder | 1 | 1 | 480 | |
| Encoder/Decoder | 1 | 1 | 440 | |
| 128-bit | Encoder | 1 | 0 | 425 |
| Decoder | 1 | 0 | 250 | |
| Encoder/Decoder | 1 | 0 | 210 | |
| Encoder | 1 | 1 | 425 | |
| Decoder | 1 | 1 | 400 | |
| Encoder/Decoder | 1 | 1 | 360 | |
Latency
The latency of the signals of the ECC core varies for different configurations. Refer to Latency for more details.