The ECC core supports Input Registering, Output Registering and Internal Pipeline Registering options. Each of these registering stages can be independently enabled during core generation. The clock cycle latency of the core equals the number of registering stages selected. There is no clock cycle latency when none of the registering stages are selected; in this case the core latency is determined by logical delay of the core. For more details on ECC core delays, refer to Maximum Frequencies.
When Clock Enable is used with the registering stages, ECC core operations are synchronous to both ECC clock and ECC Clock Enable. In this case, clock cycle latency of the core equals the number registering stages only when both clock and clock enable are asserted High.
The following figure provides the timing diagram for ECC Encoder function with a single stage of registering. With the clock-enable signal set to high, the calculated check bits and data appear at the next rising edge of the clock. The clock enable feature, when enabled, allows to control when encoded data must appear on the output port.
The following figure provides the timing diagram for ECC Decoder function with two stages of registering The data corrected for any single bit error and status outputs appears after two rising edges of the clock. The clock enable feature is used to perform each ECC operation in two clock cycles.
The following figure provides timing diagram for ECC Encoder/Decoder function with three
stages of registering. When ecc_encode input is asserted High, ECC Encoder
operations are performed on the input data and the calculated check bits and data appear
after three rising edges of the clock. When ecc_encode input is de-asserted
ECC Decoder operations are performed on input data and check bits, the data corrected for
any single bit error and status outputs appears after three rising edge of the clock.