The customizable ECC core provides multiple registering options to the user. You can set the frequency at which the core needs to operate. Based on the required frequency, select the appropriate pipeline or input/output registering option. Each registering stage impacts the latency of the core by one clock cycle.
The clock enable functionality can be used when one or more registering stages are enabled for the core. The clock enable function allows the core to perform operations only when both clock and clock enable are asserted High. Based on the synchronous elements gated by a common clock enable in the design, the ECC core can also be constrained with the clock enable period instead of applied clock period.