- Supports Single Bit Error correction and double bit error detection functions
- Supports hamming algorithm for 4 to 64 data widths
- Supports Hsiao algorithm for 4 to 128 data widths
- Supports encode only, decode only and encode/decode modes
- Supports clock enable and synchronous active-High reset
- Provides option to add input/output registering stages
- Provides optional internal pipelining stage for high frequency operations
- Supports dynamically enabling or disabling error correction function
- Provides Single Bit Error corrected and two bit error detected status outputs