The following table details the ECC core global signals.
| Port Name | I/O | Description |
|---|---|---|
| ecc_clk | I | ECC Clock. Applicable when one or more registering stages are enabled for the core. ECC core operations are synchronous to ecc_clk signal. |
| ecc_clken | I | ECC Clock Enable. Applicable when one or more registering stages are enabled for the core. When ecc_clken is used, ECC core operations are synchronous to ecc_clk clock and ecc_clken. |
| ecc_reset | I | ECC Reset. Applicable when one or more registering stages are enabled for the core. This signal is synchronous and active-High. |