The ECC core supports multiple registering options. These options include input registering, output registering and an optional internal pipeline registering stage. Each registering stage can be independently enabled. The internal pipeline registering stage breaks the computation logic into two parts and can be used for higher data widths for frequency optimization. In addition, the clock enable can be used to save power. When one or more registering stages are enabled and when clock enable is used, the ECC core pipelines the data with respect to the clock enable.