Single Error Correction and Double Error Detection (SEC-DED) error correction codes (ECC) are used to increase reliability against soft errors from random noise. As technology has scaled, the decreasing supply voltages and increasing interface speeds has resulted in reduced noise margins. This margin reduction increases the probability of soft errors introduced in both on-chip and off-chip FPGA components. For FPGA internal memory and external memories, error correction codes are needed to reduce radiation induced soft errors or single event upsets (SEU). For maintaining signal integrity, high-speed off-chip interfaces such as multi-gigabit transceivers also require increased protection against bit errors introduced due to the clock jitter or random noise. The ECC core increases system reliability under these random error conditions by detecting and correcting all single-bit errors. In addition, it detects double-bit errors in the data.