This section contains information about constraining the core in the AMD Vivado™ Design Suite.
Required Constraints
The ECC core constraints can be applied from the top-level constraints file. Clock constraint can be applied when one or more registering stages are selected for the core. Max delay constraint can be applied in case none of the registering stages are selected for the core.
Device, Package, and Speed Grade Selections
Refer to IP Facts for details about supported devices.
Clock Frequencies
This section is not applicable for this IP core.
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.