The following figure shows the Vivado IDE for the ECC core.
Figure 1. ECC in the Vivado IDE
- Algorithm Option
- Selects Hamming or Hsiao algorithms for ECC operations. The algorithm selected must be the same for encoder and decoder cores for ECC encoding and subsequent decoding operations.
- ECC Mode
- Selects Encoder, Decoder or Encoder/Decoder operations of the ECC core.
- Data Width
- Configures the width of data in bits for ECC operations. The valid range for data width
is 4 to 64 bits for Hamming and 4 to 128 bits for HSIAO algorithm.
The following table provides the minimum number of check bits required for the configured data width in bits.
Table 1. Minimum Check Bits Utilization Data Width (Bits) Minimum Check Bits 4 4 5-11 5 12-26 6 27-57 7 58-64 8 65-128 9 - Enable Input Registering
- When selected, the ECC core registers all of its inputs.
- Enable Pipeline Registering
- When selected, the ECC core inserts an internal pipeline register stage to the core.
- Enable Output Registering
- When selected, the ECC core registers all of its outputs.