AXI IIC Bus Interface LogiCORE IP Product Guide (PG090) - 2.1 English

Document ID: PG090
Release Date: 2024-12-18
Version: 2.1 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Functional Description
Multi-Master Operation
Signal Filtering
Applications
Licensing and Ordering
Product Specification
Standards
Performance
Resource Use
I/O Signals
Register Space
Global Interrupt Enable (GIE)
Interrupt Status Register (ISR)
Interrupt(0): Arbitration Lost
Interrupt(1): Transmit Error/Slave Transmit Complete
Interrupt(2): Transmit FIFO Empty
Interrupt(3): Receive FIFO Full
Interrupt(4): IIC Bus is Not Busy
Interrupt(5): Addressed as Slave
Interrupt(6): Not Addressed as Slave
Interrupt(7): Transmit FIFO Half Empty
Interrupt Enable Register (IER)
Soft Reset Register (SOFTR)
Control Register (CR)
Status Register (SR)
Transmit FIFO (TX_FIFO)
Receive FIFO (RX_FIFO)
Slave Address Register (ADR)
Slave 10-Bit Address Register (TEN_ADR)
Transmit FIFO Occupancy Register (TX_FIFO_OCY)
Receive FIFO Occupancy Register (RX_FIFO_OCY)
Receive FIFO Programmable Depth Interrupt Register (RX_FIFO_PIRQ)
General Purpose Output Register (GPO)
Timing Parameter TSUSTA Register (TSUSTA)
Timing Parameter TSUSTO Register (TSUSTO)
Timing Parameter THDSTA Register (THDSTA)
Timing Parameter TSUDAT Register (TSUDAT)
Timing Parameter TBUF Register (TBUF)
Timing Parameter THIGH Register (THIGH)
Timing Parameter TLOW Register (TLOW)
Timing Parameter THDDAT Register (THDDAT)
Designing with the Core
IIC Protocol and Electrical Characteristics
Protocol for Address and Data Transfer
Electrical Issues
Interrupts
Throttling
Programming Sequence
Standard Controller Logic Flow
IIC Master Transmitter with a Repeated Start
IIC Master Receiver with a Repeated Start
IIC Slave Receiver
IIC Slave Transmitter
Dynamic Controller Logic Flow
Start and Repeated Start Sequence
Stop Sequence
Pseudo Code for Dynamic IIC Accesses
Initialization
Read Four Bytes from an IIC Device Addressed as 0x34
Write Four Bytes (0x89, 0xAB, 0xCD, 0xEF) to an IIC Slave EEPROM Device Addressed as 0x34
Read Four Bytes from an IIC Slave EEPROM Device Addressed as 0x34
Timing Diagrams
Clocking
Resets
Design Flow Steps
Customizing and Generating the Core
IIC Parameters
Other Parameters
User Parameters
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Overview
Implementing the Example Design
Example Design Directory Structure
Simulating the Example Design
Setting Up the Simulation
Simulation Results
Test Bench
Migrating and Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for AXI IIC Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debug
Interface Debug
AXI4-Lite Interfaces
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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