Test Bench - 3.0 English - PG085

A behavioral Verilog test bench wraps around the example design top leve when the example design output product generates. The test bench provides clocking and reset stimulus to the example design top level to run simulations on the example design. It monitors the done output to signal simulation completion. The test bench is useful for getting familiar with the signaling on the core by observing the simulation waveforms. You can use the test bench with all simulation outputs from behavioral RTL through post-implementation timing.

In the example design, the simulation sources file set includes the test bench. To run the test bench, select Run Simulation in the AMD Vivado™ Flow Navigator. When the simulation is open, enter the run all command to run the simulation to completion. If the simulation completes successfully, output similar to the following code generates.

1937.60ns: exdes_tb: Starting testbench
2017.60ns: exdes_tb: Asserting reset for 16 cycles
2097.60ns: exdes_tb: Reset complete
68480.00ns: exdes_tb: SIMULATION PASSED
68480.00ns: exdes_tb: Test Completed Successfully

For more information with running the simulation test bench, see Vivado Design Suite User Guide: Logic Simulation (UG900).