Overview of Features - Overview of Features - 3.0 English - PG085

The AXI4-Stream Infrastructure IP Suite consists of eight modular IP cores supporting the AXI4-Stream specification. Common features include:

AXI4-Stream compliant

• Supports all AXI4-Stream defined signals: TVALID, TREADY, TDATA, TSTRB, TKEEP, TLAST, TID, TDEST, and TUSER.
• TDATA, TSTRB, TKEEP, TLAST, TID, TDEST, and TUSER are optional.
• Programmable TDATA, TID, TDEST, and TUSER widths (TSTRB and TKEEP width is TDATA width/8).
• ACLK/ARESETn ports.
• Per port ACLKEN inputs (optional).

AXI4-Stream Broadcaster

• Replicates a master stream into multiple output slave streams.
• Provides TDATA / TUSER remap functionality.
• Supports 2-16 slaves.

AXI4-Stream Clock Converter

• Supports low latency and area synchronous 1:N and N:1 clock conversion.
• Supports asynchronous clock conversion.
• Supports configurable ACLKEN conversion.

AXI4-Stream Combiner

• Combines multiple "narrow" streams into one wide output stream.
• Supports 2-16 masters.
• Supports error detection for unmatched TLAST, TID, or TDEST signals slave interfaces.

AXI4-Stream Data FIFO

• Supports FIFO depths from 16-32,678 in powers of 2.
• Supports Distributed RAM, Block RAM, and UltraRAM (on select devices) memory primitive types.
• Uses Xilinx Parameterized Macros for automatic constraint generation and FIFO implementation.
• Supports independent read/write clocks and ACLKEN conversion.
• Supports Packet Mode (Store and Forward based on TLAST).
• Supports error correction code (ECC) with optional ECC error injection inputs.
• Optional FIFO Flags: write data count, almost full, programmable full, read data count, almost empty, and programmable empty.

AXI4-Stream Data Width Converter

• Supports 1:N TDATA width size increase in a single stage.
• Supports N:1 TDATA width size decrease in a single stage.
• Supports arbitrary M:N TDATA width conversion in multiple stages.

AXI4-Stream Register Slice

• Allows pipelining of AXI4-Streams.
• Provides timing isolation.
• Optional pipelining to cross super logic regions (SLRs) in stacked silicon interconnect (SSI) devices.

AXI4-Stream Subset Converter

• Provides TDATA / TUSER remap functionality.
• Allows streams with different signal sets to be connected.
• Can generate a programmable TLAST.
• Can tie-off unused signals from masters.
• Can add signals based on default value rules.

AXI4-Stream Switch

• Supports 1-16 slaves.
• Supports 1-16 masters.
• Has slave side arbitrated crossbar switch.
• Supports multiple arbitration tuning points:
  • Ability to arbitrate based on TLAST.
  • Ability to arbitrate based on number of transfers.
  • Ability to arbitrate based on a timeout (counts number of consecutive LOW TVALID cycles).
• Supports Round-Robin, True Round-Robin, and Fixed Priority arbitration choices.
• Supports sparse connectivity.
• Supports routing based on TDEST base/high pairs OR optional control register routing with AXI4-Lite interface.

AXI4-Stream Interconnect

Note: Requires AMD Vivado™ IP integrator.

• Supports 1-16 slaves.
• Combines AXI4-Stream Switch with buffering modules, AXI4-Stream Data Width Converter and AXI4-Stream Subset Converter to allow masters and slaves with varying AXI4-Stream characteristics to exchange AXI4-Stream transfers.