The following table lists the signals associated with each master interface. If the
number of interfaces is configurable, the signals are then replicated for each port.
The nn denoted for the signals starts at 00 and increments by one
up to 15 for each master interface instantiated. For IPs that contain only one
master interface the nn value is dropped. For example, the
Mnn_AXIS_TVALID would be M_AXIS_TVALID. IPs
that do not support multiple clocks do not have the Mnn_AXIS_ACLK,
Mnn_AXIS_ARESETN, or the Mnn_AXIS_ACLKEN
signals.
| Signal | Direction | Description |
|---|---|---|
| mnn_axis_aclk | Input | Clock signal. All inputs/outputs of this bus interface are rising edge aligned with this clock. |
| mnn_axis_aresetn | Input | Active-Low synchronous reset signal |
| mnn_axis_aclken | Input | Clock enable signal |
| mnn_axis_tvalid 1 | Output |
TVALID indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted. |
| mnn_axis_tready 1 | Input | TREADY indicates that the slave can accept a transfer in the current cycle. |
|
mnn_axis_tdata [(c_mnn_axis_tdata_width-1):0] 1 |
Output | TDATA is the primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes. |
|
mnn_axis_tstrb [((c_mnn_axis_tdata_width/8)-1):0] 1 |
Output | TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. |
|
mnn_axis_tkeep [((c_mnn_axis_tdata_width/8)-1):0] 1 |
Output |
TKEEP is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes and can be removed from the data stream. |
| mnn_axis_tlast 1 | Output | TLAST indicates the boundary of a packet. |
|
mnn_axis_tid [c_native_tid_width-1:0] 1 |
Output | TID is the data stream identifier that indicates different streams of data. |
|
mnn_axis_tdest [(c_native_tdata_width-1):0] 1 |
Output | TDEST provides routing information for the data stream. |
|
mnn_axis_tuser [(c_snn_axis_tuser_width-1):0] 1 |
Output | TUSER is user-defined sideband information that can be transmitted alongside the data stream. |
| axis_rd_data_count[31:0] | Output |
AXI4-Stream Data FIFO Only. Indicates the read count inside the DATA FIFO. This signal can be used when using asynchronous clocking and can be sampled on the posedge of the m_axis_aclk. |
| almost_empty | Output | Almost Empty: When asserted, this signal indicates that only one more read can be performed before the FIFO goes to empty. Not available when Packet Mode is used. |
| prog_empty | Output | Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable empty threshold value. It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value. |
| sbiterr Output | Output | Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error. This signal is asserted for the transfer in which the error was detected. |
| dbiterr Output | Output | Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted. This signal is asserted for the transfer in which the error was detected. |
|
||