General Options - General Options - 3.0 English

General Options - General Options - 3.0 English - PG085

AXI4-Stream Infrastructure IP Suite LogiCORE IP Product Guide (PG085)

Document ID

PG085

Release Date

2025-08-13

Version

3.0 English

Component Name

The base name of the output files generated for the core. Names must begin with a letter and can be composed of any of the following characters: a to z, 0 to 9, and "_".

FIFO depth

This option specifies the depth of the FIFO to be instantiated. FIFO depth can vary between 16 and 32768 (powers of 2 up to 2n for whichever value of n is the current maximum.) Large FIFO depths might not be realizable on certain devices.

Memory type

Designate the FIFO memory primitive (resource type) to use.

Allowable options:

Auto: Allow Vivado Synthesis to choose.
Distributed RAM: Distributed RAM FIFO (does not support ECC).
Block RAM: Block RAM FIFO.
UltraRAM: UltraRAM FIFO (does not support independent clocks).

Independent clocks

If set to Yes, then the S_AXIS_ACLK and M_AXIS_ACLK clock signals are assumed to be asynchronous to each other and the IP operates in asynchronous mode.

CDC (Clock Domain Crossing) sync stages

When S_AXIS_ACLK and M_AXIS_ACLK are asynchronous to each other, then this parameter specifies the number of synchronization stages to use for cross clock domain logic. Increasing this value increases the MTBF of design, but incurs increased latency and logic utilization.

Enable packet mode

This option enables the Packet Mode option of the FIFO when set to Yes. This option requires the TLAST signal to be enabled. The FIFO operation in Packet Mode is modified to store transfers until the TLAST signal is asserted. When the TLAST signal is asserted or the FIFO is full, the store transfers are presented on the AXI4-Stream master interface.

ACLKEN conversion mode

This pull-down option selects the conversion mode for the ACLKEN signal. Extra latency and logic is incurred when ACLKEN conversion is performed. The options are:

None: There are no ACLKEN signals associated with the IP.
S AXIS Only: There is an S_AXIS_ACLKEN signal associated with the S_AXIS_ACLK clock signal and no M_AXIS_ACLKEN signal.
M AXIS Only: There is an M_AXIS_ACLKEN signal associated with the M_AXIS_ACLK clock signal and no S_AXIS_ACLKEN signal.
S AXIS & M AXIS: Both clocks have ACLKEN signals associated with them.

Enable ECC

Enables both ECC Encoder and Decoder. ECC enablement only supported on Block RAM and UltraRAM primitive types.

Include ECC error injection