Extra Settings - 3.0 English - PG085

The format of the remap user parameter follows syntax similar to Verilog vector concatenation.

• The remap parameter is a comma separated list of elements.
• Each element is either a constant or a bit slice of one or more SI signals.
  • For example, if SI and MI TDATA width have the same value 32, the remap string tdata[31:0] passes the entire TDATA signal from SI to MI unmodified.
  • If the MI TDATA signal were 24 bits and the SI TDATA signal were 16 bits, a remap string of 8'b00000000,tdata[15:0] assigns a constant 0 to the upper eight bits of the MI signal and pass the SI TDATA through on the lower 16 bits.
• A bit-slice element can reference a single bit of an SI signal (for example, TDATA[0]) or a vector slice of an SI signal (for example, tdata[11:8]).
  • The index values must not exceed the indices of the SI signal.
• The same SI bit can be mapped multiple times into the MI output.
  • For example, tdata[7:0], tdata[7:0] repeats the SI TDATA least significant byte twice on MI signal.
• The combined width of the constants and the SI bit slices in the remap parameter must match the MI signal width.
• The right-most element defines the least significant bits of the MI signal and the left-most element defines the most significant bits of the MI signal.
• The remap string can reference bits of the corresponding SI signal or bits from another remappable SI signal.
  • For example, the remap string for TDATA can reference bits from the TUSER SI signal.
• Constant elements and bit-slice elements can be freely mixed in the comma separated list of elements.
  • For example, tdata[7:0],8'b00000000,tdata[15:8] is a valid expression.
• Only binary format constant elements are supported.
  • h format is not supported.
• The constant element must specify the number of bits that follow b and the number of bits that follow b must match the number of bits specified. If not, a validation error is given.
• If the SI signal width is 0, the remap string must be a constant element.
• If the MI signal width is 0, the remap string is 1'b0.
• Bit slices are only valid when the SI signal width is greater than 0.
• When using IP inside of Vivado IP integrator, both m_axis and s_axis port widths of the remapped value must be set to manual override if write_bd_tcl is used.