Constraining the Core - 3.0 English

Required Constraints

The AXI4-Stream Infrastructure IP does not generally require any additional timing constraints other than clock period constraints on its clocks inputs. When using an asynchronous clock converter, the underlying Xilinx Parameterized Macro instantiates and generates an internal constraint file to prevent timing paths crossing clock domains from causing false timing errors. Those constraints apply only to internal logic inside the AXI4-Stream Infrastructure IP and are automatically generated with the IP.

Floor Planning Constraints for AXI4-Stream Register Slice SLR Crossing Modes

When using the AXI4-Stream Register Slice core in either the SLR Crossing, SLR TDM Crossing, or Multi SLR Crossing modes, the constraints must be applied to explicitly floor plan the submodules of the core into adjacent SLRs. This ensures that the SLR crossing occurs between the intended flop-to-flop, unit-fanout, internal wires across all payload and handshake pathways within the core.

SLR Crossing and SLR TDM Crossing Modes

After synthesis, all logic and registers placed into the "source" SLR (where the AXI4-Stream master connected to the SI interface is located) contain the cell name pattern "*slr_source*". All logic and registers placed into the "destination" SLR (where the AXI4-Stream slave connected to the MI interface is located) contain the cell name pattern "*slr_dest*". Constraints that combine the instance name of the AXI4-Stream Register Slice and either of these sub-module name patterns can then be used to group all cells in the core into their respective PBLOCKs for floorplanning.

In the following example, an AXI4-Stream Register Slice instance named "my_reg" is constrained to cross a SLR boundary that exists in the target device between row Y4 (the top of the lower SLR) and row Y5 (the bottom of the upper SLR):

create_pblock master_slr
add_cells_to_pblock [get_pblocks master_slr] [get_cells -hierarchical -filter
"NAME=~*my_reg*slr_source*"]
resize_pblock [get_pblocks master_slr] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4}
create_pblock slave_slr
add_cells_to_pblock [get_pblocks slave_slr] [get_cells -hierarchical -filter
"NAME=~*my_reg*slr_dest*"]
resize_pblock [get_pblocks slave_slr] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9}

Multi SLR Crossing Mode

After synthesis, all logic and registers that need to be placed into the master-side SLR (where the AXI4-Stream master connected to the SI interface is located) contain the cell name pattern *slr_master*. All logic and registers that need to be placed into the slave-side SLR (where the AXI4-Stream slave connected to the MI interface is located) contain the cell name pattern *slr_slave*. When spanning three SLRs, all logic and registers that need to be placed into the middle SLR contain the cell name pattern *slr_middle*. When spanning four SLRs, all logic and registers that need to be placed into the middle SLR adjacent to the master contain the cell name pattern *slr_middle_master*, and all logic and registers that need to be placed into the middle SLR adjacent to the slave contain the cell name pattern *slr_middle_slave*.

Constraints that combine the instance name of the Register Slice and any of these submodule name patterns can then be used to group all cells in the core into their respective PBLOCKs for floorplanning.

In the following example, an AXI4-Stream Register Slice instance named my_reg is configured in MultiSLR Crossing mode to cross two SLR boundaries that exist in the target device.

One of the boundaries exists between row Y4 (the top of the lower SLR) and row Y5 (the bottom of the middle SLR). The other boundary exists between row Y9 (the top of the middle SLR) and row Y10 (the bottom of the upper SLR).

create_pblock lower_slr
add_cells_to_pblock [get_pblocks lower_slr] [get_cells -hierarchical -filter
"NAME=~*my_reg*slr_master*"]
resize_pblock [get_pblocks lower_slr] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4}
create_pblock center_slr
add_cells_to_pblock [get_pblocks center_slr] [get_cells -hierarchical -filter
"NAME=~*my_reg*slr_middle*"]
resize_pblock [get_pblocks center_slr] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9}
create_pblock upper_slr
add_cells_to_pblock [get_pblocks upper_slr] [get_cells -hierarchical -filter
"NAME=~*my_reg*slr_slave*"]
resize_pblock [get_pblocks upper_slr] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14}