Each AXI4-Stream Infrastructure IP module has a single clock input that must be
driven with the exception of AXI4-Stream Clock Converter and AXI4-Stream Data FIFO. These modules allow for different clocks and must have both
S_AXIS_ACLK and M_AXIS_ACLK connected.
The AXI4-Stream Clock Converter and Data FIFO allows systems with different clock domains to be designed. AXI4-Stream Clock Converter synchronous mode can be used when the endpoint IP has a phase-aligned, integer multiple clock ratio to the core switch's clock. This is often the case when the same MMCM or PLL is driving synchronous integer ratio clocks because the MMCM/PLL can also ensure phase alignment across their clock outputs. The AXI4-Stream Clock Converter and AXI4-Stream Data FIFO asynchronous clocking mode allows the attached endpoint IP to run at a completely unrelated clock frequency or phase to the core switch clock.
An optional feature for clock enables (ACLKEN ports) allows an extra level
of control for essentially gating clocks. The clock enable signals can be used to control
which clock edges are seen as real transfer cycles. Clock enables can be used for purposes
like preserving global clock buffers, debug by stepping the clock enable to step through
operational states in the system, and dynamic power savings. Clock enables can be controlled
independently on each interface port and for the core switch.
The optional AXI4-Lite control register interface operates asynchronously from the AXI4-Stream clocks.