- AXI4-Stream Clock Converter
- Provides clock crossing logic to bridge two clock domains.
- AXI4-Stream Data FIFO
- Provides a depth of 16 or deeper buffering with support for multiple clocks, ECC, different resource utilization types, and optional FIFO flags.
- AXI4-Stream Register Slice
- Creates timing isolation and pipelining master and slave using a two-deep register buffer.