AXI4-Stream Interconnect - 3.0 English - PG085

AXI4-Stream Interconnect v2.1 requires IP integrator. To access the IP, first create a Vivado project, then select Create Block Design from the Vivado Flow Navigator. In the block design canvas, select the Add IP option from the toolbar and choose AXI4-Stream Interconnect from the IP integrator IP catalog window. An AXI4-Stream Interconnect IP instance is added to the block design canvas. Double-clicking on the IP instance in the diagram opens its customization window. The user-configurable options of the AXI4-Stream Interconnect are described in the following sections.

Top-level Settings

Figure 1. Top-level Settings Tab

Number of Slave Interfaces

This parameter specifies the number of AXI4-Stream slave interfaces present on the IP. Thevalue can be between 1 and 16.

Number of Master Interfaces

This parameter specifies the number of AXI4-Stream master interfaces present on the IP. The value can be between 1 and 16.

Enable ACLKEN

If set to Yes, this parameter specifies if the optional ACLKEN signal is present with all the AXI4-Stream interfaces clocks.

Use Control Register Routing

This parameter specifies the routing mode. Control register routing enables the AXI4-Lite control register interface to handle transfer routing. If this option is set to No, then the inline TDEST value is used for routing.

Data Flow Properties

Data Flow Properties options are available to modify only if the Number of Slave Interfaces is greater than 1.

Arbitrate on Maximum Number of Transfers

This setting specifies how many transfers to count before relinquishing the granted arbitration and is passed directly to the AXI4-Stream Switch within the AXI4-Stream Interconnect instance. Consult the AXI4-Stream Switch parameter descriptions for more details on the valid value range and use of this parameter.

Arbitrate on Number of LOW TVALID Cycles

This setting allows relinquishing of a granted arbitration without a transfer and is passed directly to the AXI4-Stream Switch within the AXI4-Stream Interconnect instance. Consult the AXI4-Stream Switch parameter descriptions for more details on the valid value range and use of this parameter.

Arbitrate on TLAST Transfer

This setting allows relinquishing of a granted arbitration when a transfer with TLAST asserted is received and is passed directly to the AXI4-Stream Switch within the AXI4-Stream Interconnect instance. Consult the AXI4-Stream Switch parameter descriptions for more details on the valid value range and use of this parameter.

Arbiter Algorithm

This setting allows the selection of an arbitration algorithm and is passed directly to the AXI4-Stream Switch within the AXI4-Stream Interconnect instance. Consult the AXI4-Stream Switch parameter descriptions for more details on the valid value range and use of this parameter.

Slave Interfaces

Figure 2. Slave Interfaces Tab

Enable Register Slice

If checked, an AXI4-Stream Register slice is inserted in the SI hemisphere couplers between the Snn_AXIS interface and the AXI4-Stream Switch.

FIFO Depth

If a value greater than 0 is selected, an AXI4-Stream Data FIFO is inserted in the SI hemisphere couplers between the Snn_AXIS interface and the AXI4-Stream Switch. The selected depth of the FIFO is configured directly into the AXI4-Stream Data FIFO instance.

FIFO Packet Mode

If checked and if a FIFO depth greater than 0 is selected for Snn_AXIS, the AXI4-Stream Data FIFO's packet mode is enabled. Consult the AXI4-Data FIFO parameter descriptions for more details on packet mode operation.

Master Interfaces

Figure 3. Master Interfaces Tab

Enable Register Slice

If checked, an AXI4-Stream Register slice is inserted in the MI hemisphere couplers between the AXI4-Stream Switch and Mnn_AXIS interface.

FIFO Depth

If a value greater than 0 is selected, an AXI4-Stream Data FIFO is inserted in the MI hemisphere couplers between the AXI4-Stream Switch and the Mnn_AXIS interface. The selected depth of the FIFO is configured directly into the AXI4-Stream Data FIFO instance. Consult the AXI4-Stream Data FIFO parameter descriptions for more details on the valid range of FIFO depth.

FIFO Packet Mode

If checked and if a FIFO depth greater than 0 is selected for Snn_AXIS, the AXI4-Stream Data FIFO's packet mode is enabled. Consult the AXI4-Stream Data FIFO parameter descriptions for more details on packet mode operation.

Base TDEST and High TDEST

The routing parameters shown in the previous figure set up the decoding to route slave interface transfers to master interfaces based on the TDEST signal and are passed directly to the AXI4-Stream Switch instance within the AXI4-Stream Interconnect. Consult the AXI4-Stream Switch parameter descriptions for more details on the valid range and use of routing parameters. These parameters are not configurable when Use control register routing is set to Yes.

Advanced Options

Figure 4. Advanced Options Tab

Enable FIFO Count Ports

When Yes is selected, the data count pins of any SI and MI AXI4-Stream Data FIFO instances are made available as pins on the boundary of AXI4-Stream Interconnect, as shown in the previous figure. Two sets of data counts per FIFO are available: the read count and the write count. If the interface has enabled clock conversion, then these data counts are flopped on their respective clocks. For slave interfaces, the write data count is synchronous to the clock input for that interface and the read data count is synchronous to the ACLK global clock. For master interfaces, the read data count is synchronous to the clock input for that interface and the write data count is synchronous to the ACLK global clock.

Enable URAM Memory Type

When Yes is selected, the AXI4-Stream Data FIFO inserted inside the AXI4-Stream Interconnect gets configured with UltraRAM memory. This option is only visible for devices supporting URAM.

Synchronization Stages

Specifies the number of synchronization stages used in any asynchronous clock domain conversion couplers instantiated within the AXI4-Stream Interconnect.