The Transmit FIFO ECC Error counter register shows the transmit FIFO ECC error count. The lower 16 bits [15:0] contains the 1-bit error count and the upper 16 bits [31:16] contains 2-bit error count of the Transmit FIFO.
Bit(s) | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
31:16 | TFE2BEC | Read | 0 | Transmit FIFO ECC 2-bit error counter. On reaching maximum value of 0xFFFF, it stays there until reset. |
15:0 | TFE1BEC | Read | 0 | Transmit ECC 1-bit error counter. On reaching the maximum value of 0xFFFF, it stays there until reset. |
Figure 1. AXI4-Stream Transmit FIFO ECC Error Counter Register (Offset 0x48)
