Transmit Destination Register (TDR) - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The Transmit Destination Register shown in stores the destination address corresponding to the packet to be transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core, write the destination address into TDR first, write the packet data to the Transmit Data FIFO next, and then write the length of the packet into the TLR.

The destination address must be written to the TDR before the packet data is written to the transmit data FIFO. Writing data for multiple packets to the transmit data FIFO before writing the destination address values is not a valid sequence.

Figure 1. Transmit Destination Register (Offset 0x2C)
Table 1. Transmit Destination Register Bit Definitions
Bit(s) Name Core Access Reset Value Description
3:0 TDEST Write 0x0

Transmit Destination: The destination address of the transmit packet stored in the transmit data FIFO.

TDEST is optional when generating the core and that TDEST can be specified to be 1 to 4 bits when it is implemented (see TDEST and corresponding “Width” in .
31:4 Reserved N/A 0x0 Reserved : These bits are reserved for future definition and always return all zeros.