Transmit Data FIFO Reset Register (TDFR) - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The Transmit Data FIFO Reset Register shown below is not an actual register, but is instead a write-only address, which when written with a specific value, generates a reset for the Transmit Data FIFO. This reset does not occur until transmit activity on the TX AXI4-Stream has completed. The reset can occur only during inactive times on the TX AXI4-Stream and it affects only the transmit circuitry in this core, thereby preventing the core on the other end of the AXI4-Stream from receiving a partial packet which could potentially cause a failure condition in the latter core. The reset is applied only during the inactive times on the TX AXI4-Stream. Writing a TDFR register with other than A5 value disables the reset.

Because of this mode of operation, it is possible that if the AXI4-Stream becomes unresponsive during an AXI4-Stream transaction, a reset can never occur. For example, this might occur while waiting for the destination ready to go active in the middle of a transfer. In such cases it is necessary to use both the AXI4-Stream Reset and the S_AXI_ARESETN reset.

Note: To apply the AXI4-Stream Reset, you must write the SRR register and then assert S_AXI_ARESETN.
Figure 1. Transmit Data FIFO Reset Register (Offset 0x8)

Table 1. Transmit Data FIFO Reset Register Bit Definitions
Bit(s) Name Core Access Reset Value Description
31:0 Reset Key Write N/A

Reset Write Value .

"0x000000A5" - Generate a reset.

Others - No effect.