Revision History - 4.3 English - PG080

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)
Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The following table shows the revision history for this document.

Section Revision Summary
11/08/2023 Version 4.3
Multiple Sections Fixed discrepancies between PDF and HTML documents.
05/17/2023 Version 4.3

Features

Added ECC enable/disable option for TX and RX FIFO.
Product Specification Added the following new registers: Transmit FIFO, ECC Configuration register, Transmit FIFO ECC Error Counter register, Receive FIFO ECC Configuration register and Receive FIFO ECC Error Counter register.
Customizing and Generating the Core Added Enable ECC for Transmit, FIFO parameter and Enable ECC for Receive FIFO parameter.
Vivado IDE for AXI4-Stream FIFO Updated section.
10/30/2019 Version 4.2
IP Facts Added families to Supported Device Family and added Release Notes and Known Issues.
Vivado IDE for AXI4-Stream FIFO Added Transmit/Receive FIFO Cascade Height descriptions.
Table 1 Added Transmit/Receive FIFO Cascade Height.
05/22/2019 Version 4.2
Features Updated configurable data width.
Protocol Description Added RX FIFO note.
Transmit Data FIFO Reset Register (TDFR) Added description on inactive reset.
Receive Data FIFO Reset Register (RDFR) Added description on inactive reset.
Customizing and Generating the Core Updated supported data width for AXI4 and AXI4 Data Width.
12/05/2018 Version 4.2
Features Updated standalone driver links.
Vivado IDE for AXI4-Stream FIFO Updated section.
Table 1 Updated TX and RX FIFO Programmable Empty Threshold default value to 5.
04/06/2016 Version 4.1
Interrupt Status Register Bit Definitions Corrected section, including interrupt signal definitions and configurable data widths.
04/01/2015 Version 4.1
Table 2 Updated the read interrupt status register (ISR) value.
Table 1 Updated the Reset Values for Receive FIFO Programmable Full (RFPF) and Transmit FIFO Programmable Full (TFPF).

Updated the Transmit Length Register (TLR) width to support packets up to 8 Mbytes–4.

Updated the Transmit Length Register (TLR) to support packets up to 8388604 in length.
10/01/2014 Version 4.1
Register Space

Updated the following register definitions:

  • Transmit Data FIFO Vacancy Register (TDFV)
  • Transmit Data FIFO Data Write Port (TDFD)
  • Receive Data FIFO Occupancy Register (RDFO)
  • Receive Data FIFO Data Read Port (RDFD)
  • Transmit Length Register (Store-and-Forward Mode)
  • Transmit Length Register (Cut-Through Mode)
  • Receive Length Register (Store-and-Forward Mode)
  • Receive Length Register (Cut-Through Mode)
  • Updated AXI4 ID Width to 0-16.
  • Updated the Transmit and Receive FIFO Depth ranges to 512 - 128 k (powers of 2).
  • Offset address for TDFD and RDFD registers changed from 0x10 to 0x0000 and 0x20 to 0x1000.
Port Descriptions

Added data widths of 128, 256, and 512 for AXI4 Data Interface.
04/02/2014 Version 4.0
Register Space

Corrected the value for the Interrupt Status Register (ISR).

Changed the name of the Receive Length FIFO (RLF) register to Receive Length register (RLR).

Updated the maximum packet length of Transmit Data FIFO Data Write Port and the Receive Data FIFO Data Read Port.

Added details about Store-and-Forward and Cut-Through modes to the Receive Length and Transmit Length registers.
12/18/2013 Version 4.0
Multiple Sections Added support for AMD UltraScale architecture.
10/02/2013 Version 4.0
Multiple Sections

Added details to AMD Vivado™ Integrated Design Environment (IDE).

Added selectable transmit and receive path.

Added support for IP integrator.
03/20/2013 Version 3.0
Multiple Sections Updated core to v4.0.

Removed support for ISE Design Suite.
Debugging Updated section
12/18/2012 Version 2.0
Multiple Sections

Updated core to v3.00b and Vivado Design Suite for 2012.4.
Transmit Length Register (TLR) Updated the lengths.
Receive Length Register (RLR) Updated the lengths.
Table 1 Clarified the ports that are not used by the core.
10/16/2012 Version 1.0
Multiple Sections

Initial release as a product guide.

Replaces DS806, LogiCORE IP AXI4-Stream FIFO Data Sheet.

Changed the size of the FIFO to 508 words.

Added support for an AXI4 interface, TX cut-through mode, and a 64-bit data path.