Register Space - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

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4.3 English

The AXI4-Stream FIFO core contains the registers listed in the following table.

Table 1. Register Names and Descriptions
Register Name AXI Address Access
Interrupt Status Register (ISR) C_BASEADDR + 0x0 Read/Clear on Write 1
Interrupt Enable Register (IER)) C_BASEADDR + 0x4 Read/Write
Transmit Data FIFO Reset (TDFR) C_BASEADDR + 0x8 Write 2
Transmit Data FIFO Vacancy (TDFV) C_BASEADDR + 0xC Read
Transmit Data FIFO 32-bit Wide Data Write Port (TDFD)



C_AXI4_BASEADDR + 0x0000

Write 3
Transmit Length Register (TLR) C_BASEADDR + 0x14 Write
Receive Data FIFO reset (RDFR) C_BASEADDR + 0x18 Write 2
Receive Data FIFO Occupancy (RDFO) C_BASEADDR + 0x1C Read
Receive Data FIFO 32-bit Wide Data Read Port (RDFD)



C_AXI4_BASEADDR + 0x1000

Read 3
Receive Length Register (RLR) C_BASEADDR + 0x24 Read
AXI4-Stream Reset (SRR) C_BASEADDR + 0x28 Write 2
Transmit Destination Register (TDR) C_BASEADDR + 0x2C Write
Receive Destination Register (RDR) C_BASEADDR + 0x30 Read
Transmit ID Register 4 C_BASEADDR + x34 Write
Transmit USER Register 4 C_BASEADDR + x38 Write
Receive ID Register 4 C_BASEADDR + x3C Read
Receive USER Register 4 C_BASEADDR + x40 Read
Transmit FIFO ECC Configuration Register C_BASEADDR + 0x44 Read Write
Transmit FIFO ECC Error Counter Register C_BASEADDR + 0x48 Read Only
Receive FIFO ECC Configuration Register C_BASEADDR + 0x4C Read Write
Receive FIFO ECC Error Counter Register C_BASEADDR + 0x50 Read Only


to C_BASEADDR + 0x7C

N/A 5
  1. The latched interruptible condition is cleared by writing a 1 to that bit location. Writing a 1 to a bit location that is 0 has no effect. Likewise, writing a 0 to a bit location that is 1 has no effect. Multiple bits can be cleared in a single write.
  2. Reset if written with 0xA5.
  3. C_AXI4_BASEADDR should be used only if the Data Interface option is AXI4.
  4. Not currently supported.
  5. If read, these registers returns 0x0. Writing these registers has no effect.
  6. C_BASEADDR is defined by the interconnect when using IP integrator. When you implement a standalone core (for example, selecting from the IP catalog in Vivado), only the address signals s_axi_awaddr(5:2) and s_axi_araddr(5:2) are decoded. This results in repeating the address map of the registers every 64 hex locations. In this case, C_BASEADDR can be considered to be 0.