The AXI4-Stream FIFO core contains the registers listed in the following table.
Register Name | AXI Address | Access |
---|---|---|
Interrupt Status Register (ISR) | C_BASEADDR + 0x0 | Read/Clear on Write 1 |
Interrupt Enable Register (IER)) | C_BASEADDR + 0x4 | Read/Write |
Transmit Data FIFO Reset (TDFR) | C_BASEADDR + 0x8 | Write 2 |
Transmit Data FIFO Vacancy (TDFV) | C_BASEADDR + 0xC | Read |
Transmit Data FIFO 32-bit Wide Data Write Port (TDFD) |
C_BASEADDR + 0x10 or C_AXI4_BASEADDR + 0x0000 |
Write 3 |
Transmit Length Register (TLR) | C_BASEADDR + 0x14 | Write |
Receive Data FIFO reset (RDFR) | C_BASEADDR + 0x18 | Write 2 |
Receive Data FIFO Occupancy (RDFO) | C_BASEADDR + 0x1C | Read |
Receive Data FIFO 32-bit Wide Data Read Port (RDFD) |
C_BASEADDR + 0x20 or C_AXI4_BASEADDR + 0x1000 |
Read 3 |
Receive Length Register (RLR) | C_BASEADDR + 0x24 | Read |
AXI4-Stream Reset (SRR) | C_BASEADDR + 0x28 | Write 2 |
Transmit Destination Register (TDR) | C_BASEADDR + 0x2C | Write |
Receive Destination Register (RDR) | C_BASEADDR + 0x30 | Read |
Transmit ID Register 4 | C_BASEADDR + x34 | Write |
Transmit USER Register 4 | C_BASEADDR + x38 | Write |
Receive ID Register 4 | C_BASEADDR + x3C | Read |
Receive USER Register 4 | C_BASEADDR + x40 | Read |
Transmit FIFO ECC Configuration Register | C_BASEADDR + 0x44 | Read Write |
Transmit FIFO ECC Error Counter Register | C_BASEADDR + 0x48 | Read Only |
Receive FIFO ECC Configuration Register | C_BASEADDR + 0x4C | Read Write |
Receive FIFO ECC Error Counter Register | C_BASEADDR + 0x50 | Read Only |
Reserved |
C_BASEADDR + 0x54 to C_BASEADDR + 0x7C |
N/A 5 |
|