Receive FIFO ECC Error Counter Register - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The Receive FIFO ECC Error counter register shows the ECC error count for Receive FIFO. The lower 16 bits [15:0] stores the 1-bit error count and the upper 16 bits [31:16] stores the 2-bit error count of the Receive FIFO.

Table 1. AXI4-Stream Receive FIFO ECC Error Counter Register Bit Definitions
Bit(s) Name Core Access Reset Value Description
31:16 RFE2BEC Read 0 Receive ECC 2-bit error counter. On reaching maximum value of 0xFFFF, it stays there until reset.
15:0 RFE1BEC Read 0 Receive ECC 1-bit error counter. On reaching maximum value of 0xFFFF, it stays there until reset.
Figure 1. AXI4-Stream Receive FIFO ECC Error Counter Register (Offset 0x50)