Receive FIFO ECC Configuration Register - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

Document ID
PG080
Release Date
2023-11-08
Version
4.3 English

The Receive FIFO ECC Configuration Register shown in is not an actual register, but is instead a read-write address. Bit 0 is for resetting the Receive FIFO ECC Error counters, other bits are reserved for future use.

ECC Error counters Reset is applied as long as the bit 0 is '1'.

Table 1. AXI4-Stream Receive FIFO ECC Configuration Register Bit Definitions
Bit(s) Name Core Access Reset Value Description
31:1 N/A Read 0 These bits are reserved for future definition and always return all zeros.
0 RFREEC Read/Write 0

Receive FIFO Reset ECC error counters:

Reset ECC error counters for Receive FIFO.

Write 1 to clear the Receive FIFO ECC Error counters. Counters are cleared as long as this bit is '1'.

Figure 1. AXI4-Stream Receive FIFO ECC Configuration Register (Offset 0x4C)