Receive Destination Register (RDR) - 4.3 English

AXI4-Stream FIFO LogiCORE IP Product Guide (PG080)

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4.3 English

The Receive Destination Register shown in retrieves the destination address corresponding to the valid packet received.

The RDR should only be read when a receive packet is available for processing (the receive occupancy is not zero). After the RDR is read, the receive packet data should be read from the receive data FIFO before the RDR is read again. The RDR values are stored in the receive data FIFO by the AXI4-Stream FIFO core with the data of each packet. The RDR value for the subsequent packet to be processed is moved to the RDR when the previous RDR value has been read.

Figure 1. Receive Destination Register (Offset 0x30)

Table 1. Receive Destination Register Bit Definitions
Bit(s) Name Core Access Reset Value Description
3:0 RDEST Read 0x0

Receive Destination : The destination address of the receive packet stored in the receive data FIFO.

TDEST is optional when generating the core and that TDEST can be specified to be 1 to 4 bits when it is implemented (see TDEST and corresponding “Width” in .
31:4 Reserved N/A 0x0 Reserved : These bits are reserved for future definition and always return all zeros.